This application claims benefit of priority under 35USC xc2xa7119 to Japanese Patent Application No. 2000-137098, filed on May 10, 2000, the contents of which are incorporated by reference herein.
1. Field of The Invention
The present invention relates generally to a semiconductor memory device. More specifically, the invention relates to a ferroelectric memory for storing data in a nonvolatile manner using a memory cell comprising a ferroelectric capacitor and a transistor.
2. Description of Related Art
At present, semiconductor memories are utilized in many fields, such as main memories of large computers, personal computers, various appliances and portable telephones. As semiconductor memories, volatile DRAMS and SRAMs, and non-volatile mask ROMs and EEPROMs are on the market. In particular, DRMMs are excellent in respect of low costs and high speed performance in spite of the volatile, and occupy most of the memory market. EEPROM flash memories, which are electrically rewritable non-volatile memories, are not on the market as much as DRAMs since there are disadvantages in that the number of rewriting operations are limited to about 106, that a writing time of micro seconds is required and that a high voltage is required for carrying out a writing operation.
On the other hand, ferroelectric memories (ferroelectric RAMs) using ferroelectric capacitors are widely noticed as non-volatile memories having high speed performance since they were proposed in 1980. That is, ferroelectric memories have advantages in that they store binary data in a nonvolatile manner in accordance with the magnitude of remnant polarization, that the number of rewriting operations is about 1012 and that the writing/reading time is substantially the same as that in DRAMs, so that there is some possibility that ferroelectric memories may change the semiconductor memory market. For that reason, manufacturers have competed with each other in developing ferroelectric memories, and 4-Mbit ferroelectric memories have been presented in societies.
FIG. 35 shows the circuit construction of a conventional ferroelectric memory. Similar to DRAMs, a memory cell comprises an NMOS transistor and a ferroelectric capacitor connected thereto in series. This memory cell configuration is called the 1T1C configuration. The difference from DRAMs is that data are stored in a nonvolatile manner by utilizing the remnant polarization of the ferroelectric capacitor. Similar to DRAMs, the configuration of a cell array may also be a folded bit configuration shown in FIG. 35. Similar to DRAMs, the theoretical lower limit of the minimum cell size is 2Fxc3x974F=8F2 assuming that the minimum working dimension is F.
FIG. 36 shows the operation waveform of a ferroelectric memory. In the stand-by state, bit lines BL and /BL are precharged to Vss, and plate lines PL0 and PL1 also have Vss. In the active state, the bit lines BL and /BL are first floated, an H level potential Vpp is applied to a selected word line WL, and the voltage of a selected plate line PL0 is raised from Vss to Vaa. The Vaa is a common power supply voltage in the array, and usually an external power supply voltage Vdd or a voltage dropping therefrom.
At this time, a voltage is applied to the ferroelectric capacitor of the selected cell using a bit line capacity CB as a load capacity, so that a signal charge is read out to the bit lines. The potential read out to the bit lines varies in accordance with xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d of cell data. When the data is xe2x80x9c1xe2x80x9d, the inversion of polarization occurs, so that a large potential is generated in the bit lines. When the data is xe2x80x9c0xe2x80x9d the inversion of polarization does not occur, so that a small potential variation appears in the bit lines. In the case of the 1T1C configuration, a reference potential is set to be the intermediate potential between the bit line potential in the case of the data of xe2x80x9c0xe2x80x9d and bit line potential in the case of the data of xe2x80x9c1xe2x80x9d, to sense the data by means of a sense amplifier. That is, after the data is read out to the bit lines, a sense amplifier activating signal SEN is raised to H, so that the xe2x80x9c1xe2x80x9d data is amplified to Vaa and the xe2x80x9c0xe2x80x9d data is amplified to Vss.
The destructive reading of the xe2x80x9c1xe2x80x9d data is carried out in which the inversion of polarization occurs. In the cell of the xe2x80x9c1xe2x80x9d data, after the read data is sensed, the bit lines have Vaa, and the voltage between terminals of the ferroelectric capacitor is substantially zero. Thereafter, when the voltage of the plate line is returned to Vss, a voltage Vaa having the reversed polarity to the polarity during a reading operation is applied to the ferroelectric capacitor, so that the destructively read data xe2x80x9c1xe2x80x9d is rewritten. In the cell of the xe2x80x9c0xe2x80x9d data, the bit lines have Vss, so that the voltage Vaa is applied to the ferroelectric capacitor from the side of the plate line. When the voltage of the plate line is returned to Vss, the voltage between terminals of the ferroelectric capacitor is zero, the state of the memory returns to the original remnant polarization state. Thereafter, the level of the word line WL0 is lowered, and the voltage of the bit lines BL and /BL is returned to Vss, so that the state of the memory returns to the stand-by state.
FIGS. 39A and 39B show the locus of voltages applied to a ferroelectric capacitor during the reading and writing operations when Vaa=2.5 V, respectively. In FIGS. 39A and 39B, the positive axis of abscissas shows applied voltages when the potential of a plate-line-side terminal is positive, and the negative axis thereof shows applied voltages when the potential of a bit-line-side terminal is positive. The reading voltage to the bit line is derived as a voltage (on the basis of xe2x88x922.5 V as a reference) at the intersection between the hysteresis curve of the ferroelectric capacitor and the straight load line of a bit line capacity CB, with respect to xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d data, respectively. The reason why this is obtained is that when the positions on Y-axis (the axis of the quantity of polarization) with respect to the start point of the locus of the ferroelectric capacitor and the start point of the straight load line are allowed to be coincident with each other, the charge outputted to the variation in polarization by applying a voltage to the ferroelectric capacitor is equal to the charge (CBxc3x97voltage) required to raise the bit line potential.
Specifically, in the example of FIGS. 39A and 39B, when CB=200 fF and Vaa=2.5 V, the charge read in the bit lines is about 1.5 V in the case of the xe2x80x9c1xe2x80x9d data and about 0.7 V in the case of the xe2x80x9c0xe2x80x9d data. In the case of the memory cell having the 1T1C configuration shown in FIG. 35, the intermediate value therebetween is set to be the reference voltage, the substantial signal quantity is 0.35 V. When a memory cell comprises two NMOS transistor and two ferroelectric capacitors (this will be hereinafter referred to as the 2T2C configuration), the signal quantity if 0.7 V.
Thus, in the ferroelectric memory, there is a problem in that the voltage applied to the ferroelectric capacitor is limited to the capacity ratio including the polarization of the ferroelectric capacitor to the bit line capacity. Specifically, in the example of FIG. 39, the voltage applied to the ferroelectric capacitor during reading is 2.5 Vxe2x88x921.5 V=1.0 V in the case of the xe2x80x9c1xe2x80x9d data. In the case of the xe2x80x9c0xe2x80x9d data, the voltage is 2.5 Vxe2x88x920.7 V=1.8 V. If the cell array power supply voltage Vaa is applied to the ferroelectric capacitor as it is, the difference in signal corresponding to the difference (2Pr=2xc3x97200 fF) between the quantities of remnant polarization in the cases of the xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d data can be obtained. However, the bit line capacity CB is limited, only a voltage less than Vaa is applied to the ferroelectric capacitor. In other words, only a part of remnant polarization contributes to the signal.
On the other hand, in the case of a writing (rewriting) operation, if the capacity of the plate line is sufficiently large, the amplified voltage of the bit lines is applied to the ferroelectric capacitor as it is, so that substantially 100% of the power supply voltage Vaa is applied to the ferroelectric capacitor as shown in FIG. 39B. The fact that the voltage applied to the ferroelectric capacitor is low has the merits of having a small deterioration due to fatigue. However, the fatigue is determined by the writing (rewriting) operation in which the high voltage Vaa is applied (the fatigue specification of the ferroelectric memory is determined by the total number of cycles of reading/writing operations).
The above described problem is not practically a serious problem in a ferroelectric capacitor on standard conditions that the sufficient reading signal quantity shown in FIGS. 39A and 39B can be obtained. However, there is a serious problem (1) if the hysteresis characteristics of the respective cells vary, (2) if a deterioration due to depolarization is great, (3) if a decrease in signal due to an imprint is great, (4) if a deterioration due to fatigue is great, or (5) if the power supply voltage is lowered. The problem is particularly serious since the influence of the shift of the hysteresis curve due to the imprint is conspicuous when the value of Vaaxe2x80x94(anti-voltage after imprint) is low.
FIG. 40 shows the state of the deterioration of a signal when the power supply voltage Vaa drops from 3 V to 2.5 V. Assuming that the anti-voltage is Vc, the signal quantity greatly decreases due to the decrease of Vaa since the signal quantity is in proportion to Vaaxe2x88x92Vc. In addition thereto, as shown in the locus during the reading of the xe2x80x9c1xe2x80x9d data, the variation in polarization end decreases, so that the remnant polarization is not more effectively utilized.
As described above, when the bit line capacity CB is relatively small, the voltage applied to the ferroelectric capacitor during the reading of data is small. on the other hand, when the bit line capacity CB is sufficiently large, a high voltage is applied to the ferroelectric capacitor, but the reading signal quantity is small.
In addition to the above described problems, the conventional ferroelectric memory has disadvantages in that the size of the cell can not be smaller than that of a DRAM, that the resistance of the plate line increases since it is required to divide a plate line every word line, and that since it is required to arrange a plate line driving circuit at the pitch of word lines, it is not possible to obtain a sufficient driving capacity, the operation speed is lower than that of DRAMs. The inventors have proposed a ferroelectric memory capable of eliminating the above described disadvantages (Japanese Patent Application Nos. 8-147452 , 9-001115 , 9-153137, 9-346404, etc.).
FIG. 37 shows the construction of the above described ferroelectric memory. Each of memory cells comprises a parallel-connected circuit consisting of an NMOS transistor and a ferroelectric capacitor. The plurality of parallel-connected circuits are chain-connected in series to constitute a memory block. One end of the memory cell block is connected to bit lines via block selecting NMOS transistors, and the other end thereof is connected to plate lines. With this construction, there are advantages in that (1) it is possible to obtain a small unit memory size of 4F2, (2) a plane transistor capable of being easily produced is used, (3) it is possible to carry out a general purpose random access, and (4) it is possible to carry out a rapid reading/writing operation.
FIG. 38 shows the operation waveform of such a ferroelectric memory. In a stand-by state, all of the word lines are held so as to have a H level, a block selecting signal is held so as to have a L level, and both ends of the ferroelectric capacitor are short-circuited to stably hold data. In an active state, a selected word line, e.g., WL0, is set so as to have a L level, the bit line precharged to Vss is set so as to be floating, a block selecting signal, e.g., BS0, is set so as to have a H level, and Vaa is applied to a selected plate line PL0. Thus, a voltage is applied to a ferroelectric capacitor of a memory cell which is selected in the same manner as that in usual ferroelectric capacitors, so that a reading operation is carried out. The transistors of unselected memory cells in a selected block remain being turned on, so that no voltage is applied to the ferroelectric capacitor, thereby holding data. However, the basic operation of this ferroelectric memory is the same as that of the conventional ferroelectric memory, the problem in that a sufficient voltage is not applied to a ferroelectric capacitor during a reading operation remains.
As described above, in the conventional ferroelectric memory, there is a problem in that a sufficient voltage is not applied to a ferroelectric capacitor during a reading operation as compared with a writing operation, so that accumulated information on remnant polarization is not sufficiently read, thereby causing a reading signal quantity to be small. In particular, when an operation is carried out at a low voltage, this problem is serious, and the deterioration of a signal due to an imprint is conspicuous.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a ferroelectric memory capable of sufficiently reading information on remnant polarization.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory device comprises: a memory cell array wherein memory cells, each of which comprises a ferroelectric capacitor and a transistor, are arranged and wherein word lines for selecting the memory cells, plate lines for applying a driving voltage to one end of the ferroelectric capacitor, and bit lines, to which the other end of the ferroelectric capacitor is selectively connected, are provided; a sense amplifier for detecting and amplifying a signal which is read out from the ferroelectric capacitor to the bit line; and a bit line voltage control circuit, connected to the bit lines, for dropping a voltage of a bit line, from which a signal is read out, during a data reading operation before the sense amplifier circuit is operated.
According to the present invention, the voltage applied to the ferroelectric capacitor is raised during a data reading operation by dropping a bit line voltage during the data reading operation, so that it is possible to effectively read information on remnant polarization. Specifically, according to the present invention, the bit line voltage control has at least one capacitor for dropping the voltage of the bit line by a capacitive coupling to the bit line. Alternatively, the bit line voltage control circuit has a pair of capacitors, each of which is provided in a corresponding one of a pair of bit lines and each of which is driven so as to be connected to a selected bit line of the pair of capacitors.
More specifically, the above described bit line voltage control circuit may have any one of the following constructions.
(a) The bit line voltage control circuit may have a pair of capacitors, each of which is provided in a corresponding one of a pair of bit lines, a first terminal of each of the pair of capacitors being connected to a corresponding one of the pair of bit lines, and a second terminal of each of the pair of capacitors being connected to a corresponding one of a pair of driving signal lines, a first potential being applied to the pair of driving signal lines before a data reading operation, and a second potential which is lower than the first potential being applied to one of the pair of driving signal lines during the data reading operation.
(b) The bit line voltage control circuit may have first and second transistors, the drain of each of the first and second transistors being connected to a pair of bit lines, and a capacitor, one end of which is connected to the sources of the first and second transistors and the other end of which is connected to a driving signal line, a first potential being applied to the driving signal line and the first and second transistors being turned on before a data reading operation, and one of the first and second transistors on the side of an unselected bit line being turned off and a second potential which is lower than the first potential being applied to the driving signal line during the data reading operation.
(c) The bit line voltage control circuit may have a first transistor, the drain of which is connected to the bit line, a capacitor, one end of which is connected to the source of the first transistor and the other end of which is connected to a driving signal line, and a second transistor which is provided between a connection node of the first transistor to the capacitor and a power supply line of a first potential, a second potential which is higher than the first potential being applied to the driving signal line, the first transistor being turned off and the second transistor being turned on before a data reading operation, and the second transistor being turned off and the first transistor being turned on to apply a third potential, which is lower than the second potential, to the driving signal line during the data reading operation.
The coupling capacitor for use in each of the above described bit line voltage control circuits preferably has a capacity which is 10% or more as large as the capacity of the bit line.
According to another aspect of the present invention, a semiconductor memory device comprises:
a memory cell array wherein memory cells, each of which comprises a ferroelectric capacitor and a transistor, are arranged and wherein word lines for selecting the memory cells, plate lines for applying a driving voltage to one end of the ferroelectric capacitor, and bit lines, to which the other end of the ferroelectric capacitor is selectively connected, are provided; a sense amplifier for detecting and amplifying a signal which is read out from the ferroelectric capacitor to the bit line; and a plate line driving circuit for applying a voltage, which has a greater amplitude than an amplitude voltage of the bit line, to the plate line during a data reading operation before the sense amplifier circuit is operated.
Thus, by applying the great amplitude voltage to the plate line during the data reading operation, the voltage applied to the ferroelectric capacitor during the data reading operation can be raised similar to the case where the voltage of the bit line is dropped, so that it is possible to effectively read information on remnant polarization.
In this case, the plate line driving circuit preferably applies a voltage, which has the same amplitude as the amplitude voltage of the bit line, to the plate line when the sense amplitude circuit is operated. For example, the plate line driving circuit may comprise: a resetting transistor for resetting the plate line at a reference voltage; a first driving transistor for selectively applying a voltage, which has the same amplitude as the amplitude voltage of the bit line, to the plate line; and a second driving transistor for selectively applying a voltage, which has a greater amplitude than the amplitude voltage of the bit line, to the plate line.
Alternatively, the plate line driving circuit may comprise: a capacitor, one end of which is connected to the plate line; a resetting transistor for resetting the plate line at a reference voltage; a precharging transistor for precharging a voltage, which has the same amplitude as the amplitude voltage of the bit line, to the capacitor; and a booster driving circuit for selectively driving the other end of the capacitor to apply a voltage, which has a greater amplitude than the amplitude voltage of the bit line, to the plate line.
The memory cell array of the semiconductor memory device, to which the present invention is applied, may have a unit memory cell comprising a ferroelectric capacitor and a transistor connected to the ferroelectric capacitor in series, or may form a memory block wherein a plurality of circuits, each of which comprises a ferroelectric capacitor and a transistor connected thereto in parallel, are connected in series between the bit line and the plate line.